Digital integrated circuits are usually comprised of a large number of individual circuit elements which may be combinational in nature, such as a gate, or sequential in nature, such as a flip-flop. The testing of both the combinational and sequential circuit elements in an integrated circuit is performed by generating a pattern of test vectors and successively applying the vectors to the integrated circuit inputs. Depending on the pattern of the test vectors which are applied, the responses of the integrated circuit to the vectors can provide a very accurate indication of the faults that may be present.
Test vector selection, often referred to as test pattern generation, is a straightforward task for combinational circuit elements. However, for sequential circuit elements, test pattern generation is far more complex because of the need to propagate known values from element to element over time. To simplify the task of testing an integrated circuit containing a large number of sequential elements, there has been developed a technique known as "partial-scan testing" which is disclosed in U.S. Pat. No. 5,043,986, issued on Aug. 27, 1991, to V. D. Agrawal et al., and assigned to AT&T Bell Laboratories, the present assignee. As disclosed in that patent, partial-scan testing of an integrated circuit is practiced by first isolating a selected set of memory elements (e.g., flip-flops) within the integrated circuit and then coupling such elements in a chain. Each of the memory elements is chosen such that while the integrated circuit is in a test mode, substantially all feedback paths from an output of a chosen memory element to its input are less than a selected cycle length defined by the number of memory elements in the chain.
While in the test mode, test data is scanned into the chain of selected memory elements of the integrated circuit. Once the test data is entered, the integrated circuit is returned to a non-test mode so that the selected memory elements can respond to the previously-received test data in their usual manner. After a certain period of time, the test mode is re-entered, and the response of the selected memory elements is captured for analysis.
The partial-scan technique described in the Agrawal et al. patent can achieve very high fault coverage, even when as few as 10-30% of the memory elements are tested (i.e., scanned) in the manner described. However, partial-scan testing of individual integrated circuits carried by a circuit board is difficult to accomplish at a board level, or at a higher level, such as at a system or field level.
Thus, there is a need for a technique for testing an integrated circuit which allows for high fault coverage and also can be practiced in a built-in self-test mode on a circuit board level and beyond.